A new look at the figures around Moore’s law


“There have been morose expectations and miserable prognostics, for like 20 years,” he reasoned, because semiconductor growth has been compared with worldwide gross domestic product (GDP) for 40-50 years. Comparing the industry to GDP produced figures that were always significantly higher producing a feel-good atmosphere across the semiconductor industry. And then there was the dotcom crash in 2000 and growth in the semiconductor industry was fundamentally flat, despite a compounded growth rate of 1%-2% and even into 2010, growth improved but was still smaller than global GDP. People are talking only about growth through consolidation, he says, yet look at any chip and you can see that Moore’s law is still true. Not only is the number of transistors increasing every two years, but new uses for this capability continue to be developed.

“There is an inelegant term, digitialistion, and that indicates a pretty significant change,” he told Electronics Weekly. While electronics and semiconductor content has always been important to how an end product will look, the automotive industry in particular has used increases in electronics performance to add functionality that could not exist before. This could be the autonomous driving space, in-vehicle infotainment (IVI) or electrification of the electrification of the vehicle.

This also allows companies to alter their business models, with for example over the air (OTA) updates enabling vehicle manufacturers to offer services, including subscription ones to end customers.  As a result, systems companies, whether in the communications, space, automotive, manufacturing or medical markets, are all becoming involved with semiconductors.

He cited four main drivers: sensor technology, edge based computing, 5G and data centres. These, he said are exploding in growth to the extent that systems companies have increased from around 1% of overall foundry volume in 2001 to stand at 32% today.

“All of a sudden semiconductors have became this huge space of new opportunity and investment,” he said, with venture capital spending also “exploding” after collapsing to near zero following the 2008 recession. Evidence of this is the activity in foundry capital spending, with TSMC fabs in the US today and in Japan and Intel’s large scale programme to build fabs inside and outside of the US.

This is good news for design tool sales too. “For ages, design starts were dropping every year and now we are seeing numerous areas where that is actually increasing,” he said, citing wearables, the IoT and automotive markets as areas of particular interest. The EDA industry has seen five quarters of double-digit growth and have hit the highest growth rate we have had in the last 10 – 20 years”.

To continue this momentum, the industry will have to continue to enable technology scaling, i.e., Moore’s law and 3D. This is at the heart of part of the appeal for digitisation, he reasons. “If you start designing an architecture now, in that same amount of area and cost you can dedicate to the system 10 years from now you are going to be able to deliver x15 the capability you used to be able to deliver. That’s an incredible piece of magic”.

An example is the smartphone, it has progressed from a device for texting and sending pictures to one that performs neural processing for face recognition and augmented reality; all in the same silicon area and at approximately the same cost per die. Apple’s own figures over an eight year period show that the company is keeping to Moore’s law, he argued. In the last eight years, the company has used chips with 1bn transistors to the most recent design with 15bn transistors. In the same period, single core performance has increased by a factor of five, and GPU performance has increased around 15%-17%, he reported.

He believes the industry is looking at “very strong growth” over this decade. For that reason, Moore’s law and technology scaling will thrive. “Giving people the ability to design with twice as many transistors every two years, means you also need to deal with design scaling. You cannot afford to have that cost twice as much to design every two years because then your NREs are too high and eventually it becomes impossible to justify the NRE based on the overall volume of the chip,” he pointed out. The solution is to move to high level sysnthesis which will enable an order of magnitude greater productivity, Sawicki said.

Designers will also need to pay attention to system scaling. Sawicki said that it is not enough to design a chip that can meet a functional spec, they must also understand what that chip is going to do in conjunction with other chips, as well as the application stack. “Potentially,  in things like automotive, [they will also  – how it’s going to be handling real world interfaces out to the external environment and the car dynamics as well. That in many ways is why siemens acquired mentor because including that vision where you can do a digital twin of the full electrical- mechanical system is a critical factor to deliver on that technology.

 

Reader’s digest version of joe’s presentation .

Executive Vice President, IC EDA

Formerly responsible for Mentor’s industry-leading design-to-silicon products, including the Calibre physical verification and DFM platform and Mentor’s Tessent design-for-test product line, Sawicki now oversees all business units in the Siemens EDA IC segment.

Sawicki joined Mentor Graphics in 1990 a

ttps://www.plm.automation.siemens.com

 





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