Register memory IP cuts SoC power for wearables


Branded MiniMiser, its architecture is based on a customised storage element – rather than on the foundry bit cell – and exploits the company’s SRAM power saving techniques. Multi-port and high-performance variants can be generated.

“MiniMiser gives developers a new way of optimising the power envelope for their design,” said SureCore CEO Paul Wells. “Savings of over 50% can be delivered by swapping in MiniMiser instances. By reviewing the application’s operational demands they can further enhance this by introducing multiple performance modes tied to various operating voltages.”

Wearable devices are a potential end use, where increasing artificial intelligence is requiring more memory within a tight power budget.

Register files are small blocks of memory that typically interface directly to high performance logic to provide fast access to data. These are often located inside the related compute blocks to reduce wiring delays. Their activity level, and therefore their power dissipation, is linked to the logic they are coupled to.

“Standard off-the-shelf register file IP is usually based on the foundry bit cell, and whilst this give optimal area utilisation, the power metrics are often poor – with the bit cell itself precluding a reduction in operating voltage to tune the logic for a range of performance goals,” said SureCore CTO Tony Stansfield. “Designers are forced to implement multiple power islands – at least one for the logic and one for the memories. This introduces a level of physical design complexity plus the addition of level shifters as well as necessitating considerable care with the timing analysis strategy. Our register file architecture supports both a wide operating voltage range as well as the capability to deliver the high performance needed by AI applications.”

SureCore

 





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