RISC-V reviews progress.


RISC-V membership grew 130% in 2021 to 2,478 members including 18 Premier level members.

Engagement in RISC-V work groups and committees has grown 67% in the last year to nearly 12,000 individuals.

RISC-V anticipates that in 2021 alone there will be two billion RISC-V cores on the market.

RISC-V technical progress has benefited the community with member programs such as RISC-V Development Partners, RISC-V Labs, and RISC-V Developer Boards.

RISC-V also launched RISC-V Mentorships, and the creation of the Open Hardware Diversity Alliance.

In 2021, RISC-V continued to focus on driving progression and ratification of standards and technical deliverables.

Last week, RISC-V announced its ratification of 15 new specifications. These specifications, which include the Vector, Scalar Cryptography, and Hypervisor specifications, will help unlock new opportunities for developers creating RISC-V applications for AI, ML, the IoT, connected and autonomous cars and data centres.

In February, RISC-V unveiled its Fast Track Architecture Extension Process (Fast Track) that streamlines the ratification of small architecture extensions.

Fast Track defines the process for developing and standardizing architecture extensions that meet specific criteria, while providing reasonable quality control under the oversight and approval of the relevant RISC-V standing committee.

In correlation, the new Fast Track process ratified the first extension, ZiHintPause, which allows engineers to reduce the energy consumption of their designs, improves the performance of spin-wait loops, and enables multithreaded cores to temporarily relinquish extension resources by adding a single PAUSE instruction (encoded as a HINT instruction) to the ISA.

Additionally, RISC-V expanded its industry alliances to engage a broad community of stakeholders across both technical and non-technical topics that help the open source community and industries using RISC-V technology.

To increase the security features that encompass the ISA, seL4 Foundation and RISC-V verified seL4 microkernel on the RV64 architecture which guarantees that the microkernel will operate to specification even when built with an untrusted C compiler, GCC.

Together RISC-V and seL4’s collaboration enables stronger security, combining security-oriented architecture and operating system design.

RISC-V and CHIPS Alliance formed a newOmniXtend working group that focuses on creating an open, cache coherent, unified memory standard for multicore compute architectures to make it easier for designers to take advantage of OmniXtend for data-centric applications.

Founded in collaboration among RISC-V, CHIPS Alliance, OpenPOWER Foundation, and Western Digital, the Open Hardware Diversity Alliance was launched to provide support programs, learning opportunities, and mentorships for women and underrepresented individuals in the open hardware community.

By providing a supportive community, the program will help to drive professional growth, empower the development of technical careers, encourage the recognition of all ideas in technical innovations, and support career growth.

Together with The Linux Foundation, RISC-V launched three free online courses to empower individuals to better understand how to implement and utilize RISC-V.

The courses have been among the most popular courses in LF history with 8,842 enrollments in the first nine months.

The first course, Introduction to RISC-V (LFD110x), provides the foundational knowledge needed to effectively engage in the RISC-V community, contribute to the ISA specifications, and develop a wide range of RISC-V software and hardware projects.

The second course, Building a RISC-V CPU Core (LFD111x), focuses on digital logic design and basic central processing unit (CPU) microarchitecture and allows participants to familiarize themselves with a variety of emerging technologies supporting an open source hardware ecosystem, including RISC-V, transaction-level verilog, and the online Makerchip IDE.

The third course, RISC-V Toolchain and Compiler Optimization Techniques, is designed for RISC-V application developers looking to improve performance or reduce the code size of their applications, toolchain developers, compiler engineers/performance engineers, and computer science students aspiring to major in systems software.

 





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