Building on the earlier Performance P550 processor, company engineering estimates are that it will have 40% more performance per clock cycle – to 11+SPECInt2006/GHz – and it has architecture enhancements improve maximum clock frequency – together adding to 50% performance gain over the P550.
Performance can be scaled. Maximum is with sixteen cores in a coherent complex with platform-level memory management and interrupt control. Support is included for the new Risc-V hypervisor extension for virtualisation.
Introduction is scheduled for mid-2022, with what the company is calling an ‘architecture preview’ offered to lead customers in Q1 2022. Potential markets span “data centre to edge, automotive, compute and mobile”, it said.
Also at the Risc-V Summit in San Francisco, SiFive introduced ‘Essential 6-Series’ processor cores for mid-range application processing and real-time processing.
They are the 64bit Linux-capable Essential U6, the 64bit real-time Essential S6, and the 32bit real-time Essential E6.
“Essential 6-Series processors leverage the Essential 7-Series architecture, and feature pre-configured product specifications that may be tuned towards applications such as general-purpose embedded, industrial, IoT, high-performance real-time embedded and automotive applications,” according to the company.
For existing products, SiFive’s 21G3 release of updates was announced, introducing improved clock gating and power management, and adding Shield WorldGuard support to the Essential family. On top of this, its ‘intelligence extensions’ – as used in the Intelligence X280 – now support BFLOAT16 compute, quantisation acceleration and have improved multi-cluster support. The rest of the Performance family also get Risc-V hypervisor extensions.