TSMC running pilot 3nm wafers

The process uses EUV for more than 20 layers delivering a 10% to 15% performance gain over 5nm (at the same power and transistor count), up to 30% power reduction (at the same clocks and complexity), up to 70% logic density gain, and an up to 20% SRAM density gain.

It is reported that Intel will use its Foveros  technology to package the 3nm GPU chiplets in its Meteor Lake SoCs alongside 7nm Intel CPU chiplets.

Samsung says it will be producing wafers on its 3nm GAA process in H1 next year, and it is rumoured that AMD and Qualcomm will be its first customers for the process.

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